4 Commits

Include renames

• style: format scheduling test
  lda 2026-09-09 19:56:05 +07:00
  Verified ac560f0212
• sched: tidy schedule expression test imports
  lda 2026-09-08 10:51:58 +07:00
  Verified 7f6c832b0b
• sched: address R1 findings on shared traversal and resolver threading
  lda 2026-09-08 10:15:36 +07:00
  Verified 46c2763b66
• sched: add typed occurrence expression kind for schedule inputs (T04)
  lda 2026-09-08 10:09:31 +07:00
  Verified 0ded9b0d40